Introduction to HDLs - Electronic Engineering (MCQ) questions & answers

1)   Match the following value kind attributes with their return elements :

A. Value Type attribute -------------------- 1) Length  
B. Value Array attribute ------------------- 2) Information
C. Value Block attribute ------------------- 3) Bounds

a. A- 3, B- 1, C- 2
b. A- 1, B- 2, C- 3
c. A- 2, B- 1, C- 3
d. A- 2, B- 3, C-1
Answer  Explanation 

ANSWER: A- 3, B- 1, C- 2

Explanation:
No explanation is available for this question!
2)   Which among the following is not a type of concurrent statement?

a. Simple signal assignment
b. Selected signal assignment
c. Generate statement
d. Direct Instantiation
Answer  Explanation 

ANSWER: Direct Instantiation

Explanation:
No explanation is available for this question!
3)   Which type of logic is produced by case statements?

a. Serial logic
b. Parallel logic
c. Priority encoded logic
d. Priority decoded logic
Answer  Explanation 

ANSWER: Parallel logic

Explanation:
No explanation is available for this question!
4)   Which among the following does not belong to the category of sequential statements?

a. If statements
b. Process statements
c. Loop statements
d. Node statements
Answer  Explanation 

ANSWER: Node statements

Explanation:
No explanation is available for this question!
5)   What does an arrow indicate in the schematic format of process statement given below?

a. Variable declaration
b. Process body
c. Process label
d. Sensitivity list
Answer  Explanation 

ANSWER: Sensitivity list

Explanation:
No explanation is available for this question!
6)   How are the design specifications represented in the behavioral modeling style of VHDL?

a. Boolean equation
b. Truth table
c. Logical diagram
d. State diagram
Answer  Explanation 

ANSWER: Truth table

Explanation:
No explanation is available for this question!
7)   Dataflow style of architectural modeling is represented as a set of  ___________ assignment statements.

a. Sequential
b. Concurrent
c. Random
d. Combinational
Answer  Explanation 

ANSWER: Concurrent

Explanation:
No explanation is available for this question!
8)   Which type of architectural modeling style describes the internal design details in the form of a set representing the interconnected components?

a. Dataflow
b. Behavioral
c. Structural
d. Mixed
Answer  Explanation 

ANSWER: Structural

Explanation:
No explanation is available for this question!
9)   Which among the following is the correct way of entity representation for the two input NAND gate shown below?

a. NAND 5 entity is
port (A, B : input;
C: output);
NAND 5 end;
b. entity NAND5 is
port (A, B : in bit;
C: out bit);
end NAND 5;
c. Entity: NAND5
port(Inputs: A, B;
Output : C);
end;
d. entity : NAND5
port( inbit : A,B),
( outbit: C);
end.
Answer  Explanation 

ANSWER: entity NAND5 is
port (A, B : in bit;
C: out bit);
end NAND 5;

Explanation:
No explanation is available for this question!
10)   Which mode in VHDL allows to make the signal assignments to a port of mode out by preventing it from reading?

a. In
b. Out
c. Inout
d. Buffer
Answer  Explanation 

ANSWER: Inout

Explanation:
No explanation is available for this question!
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